'Strained silicon': How it works

By Michael Kanellos

Tinkering at the atomic level is becoming a daily issue for chip manufacturers. For decades, chip makers have steadily shrunk the size of transistors and chips by following Moore's Law, which dictates that the number of transistors on a chip doubles every two years.

Moore's Law has worked so well, though, that engineers now find themselves up against the laws of physics. The gate oxide on chips made on the 90-nanometer process, for instance, which separates the sub-elements of a transistor, will measure only five atoms across. Technically, these chips can be classified as nanotechnology parts because their components will measure less than 100 nanometers across.

Designing chips that work and can be manufactured profitably at this level requires more leaps of creativity than in the past, especially when it comes to managing power inside these devices, according to designers and engineers. Fast chips generally require greater amounts of energy. Increased electricity, though, can be detrimental to performance.

To navigate the contradictory demands, Intel redesigned the insulating materials, replacing a silicon-based material with a carbon one, between different layers of the chips with the 90-nanometer chips, Bohr said. The chips will also contain seven, rather than six, layers of transistors like current chips. Stretching the silicon, he added, will increase current flow 10 percent to 20 per cent, but increase cost only 2 per cent.

Chips made on this manufacturing process will be faster than today's microprocessors, but contain far more transistors. Prototype SRAM (static RAM) chips, a type of memory, produced by Intel contain more than 330 million transistors in a 100-millimeter square space, Bohr said. About 120 billion transistors will fit on a standard 300-millimeter wafer.

Chips made on the 90-nanometer process will first come from the company's fabs in Oregon and later from the facilities in Ireland and New Mexico, which are geared more for mass production.

Although more advanced than current chips made on 130-nanometer manufacturing techniques, the 90-nanometer chips manufacturing process will allow the company to re-use about 75 percent of today's equipment, Bohr said.

"This ensures that we will have a high-volume manufacturing ramp next year," he said.
The 90-nanometer manufacturing process, though, isn't a panacea. Chips made on this process will be more subject to gate leakage, or random energy dissipation, a phenomenon that can reduce battery life and other problems, Bohr said.

Coming up with a system for manufacturing 65-nanometer chips in 2005 will be even more difficult.

"Shrinking it (the gate oxide) to 65 nanometers is going to be pretty tough," he said.

Michael Kanellos writes for News.com